1. Field of the Invention
This invention relates to electronic systems, and more particularly to electrical interconnecting apparatus having continuous planar conductors.
2. Description of the Related Art
Electronic systems typically employ several different types of electrical interconnecting apparatus having planar layers of electrically conductive material (i.e., planar conductors) separated by dielectric layers. A portion of the conductive layers may be patterned to form electrically conductive signal lines or “traces”. Conductive traces in different layers (i.e., on different levels) are typically connected using contact structures formed in openings in the dielectric layers (i.e., vias). For example, integrated circuits typically have several layers of conductive traces which interconnect electronic devices formed upon and within a semiconductor substrate. Each layer is separated from adjacent layers by dielectric layers. Within a semiconductor device package, several layers of conductive traces separated by dielectric layers may be used to electrically connect bonding pads of an integrated circuit to terminals (e.g., pins or leads) of the device package. Printed circuit boards (PCBs) also typically have several layers of conductive traces separated by dielectric layers. The conductive traces are used to electrically interconnect terminals of electronic devices mounted upon the PCB.
Signals in digital electronic systems typically carry information by alternating between two voltage levels (i.e., a low voltage level and a high voltage level). A digital signal cannot transition instantaneously from the low voltage level to the high voltage level, or vice versa. The finite amount of time during which a digital signal transitions from the low voltage level to the high voltage level is called the rise time of the signal. Similarly, the finite amount of time during which a digital signal transitions from the high voltage level to the low voltage level is called the fall time of the signal.
Digital electronic systems are continually being produced which operate at higher signal frequencies (i.e., higher speeds). In order for the digital signals within such systems to remain stable for appreciable periods of time between transitions, the rise and fall times of the signals must decrease as signal frequencies increase. This decrease in signal transition times (i.e., rise and fall times) creates several problems within digital electronic systems, including signal degradation due to reflections, power supply “droop”, ground “bounce”, and increased electromagnetic emissions. It is desirable that digital signals be transmitted and received within acceptable tolerances.
A signal launched from a source end of a conductive trace suffers degradation when a portion of the signal reflected from a load end of the trace arrives at the source end after the transition is complete (i.e., after the rise time or fall time of the signal). A portion of the signal is reflected back from the load end of the trace when the input impedance of the load does not match the characteristic impedance of the trace. When the length of a conductive trace is greater than the rise time divided by three, the effects of reflections upon signal integrity (i.e., transmission line effects) should be considered. If necessary, steps should be taken to minimize the degradations of signals conveyed upon the trace due to reflections. The act of altering impedances at the source or load ends of the trace in order to reduce signal reflections is referred to as “terminating” the trace. For example, the input impedance of the load may be altered to match the characteristic impedance of the trace in order to prevent signal reflection. As the transition time (i.e., the rise or fall time) of the signal decreases, so does the length of trace which must be terminated in order to reduce signal degradation.
A digital signal alternating between the high and low voltage levels includes contributions from a fundamental sinusoidal frequency (i.e., a first harmonic) and integer multiples of the first harmonic. As the rise and fall times of a digital signal decrease, the magnitudes of a greater number of the integer multiples of the first harmonic become significant. As a general rule, the frequency content of a digital signal extends to a frequency equal to the reciprocal of π times the transition time (i.e., rise or fall time) of the signal. For example, a digital signal with a 1 nanosecond transition time has a frequency content extending up to about 318 MHz.
All conductors have a certain amount of inductance. The voltage across the inductance of a conductor is directly proportional to the rate of change of current through the conductor. At the high frequencies present in conductors carrying digital signals having short transition times, a significant voltage drop occurs across a conductor having even a small inductance. A power supply conductor connects one terminal of an electrical power supply to a power supply terminal of a device, and a ground conductor connects a ground terminal of the power supply to a ground terminal of the device. When the device generates a digital signal having short transition times, high frequency transient load currents flow in the power supply and ground conductors. Power supply droop is the term used to describe the decrease in voltage at the power supply terminal of the device due to the flow of transient load current through the inductance of the power supply conductor. Similarly, ground bounce is the term used to describe the increase in voltage at the ground terminal of the device due to the flow of transient load current through the inductance of the ground conductor. When the device generates several digital signals having short transition times simultaneously, the power supply droop and ground bounce effects are additive. Sufficient power supply droop and ground bounce can cause the device to fail to function correctly.
Power supply droop is commonly reduced by arranging power supply conductors to form a crisscross network of intersecting power supply conductors (i.e., a power supply grid). Such a grid network has a lower inductance, hence power supply droop is reduced. A continuous power supply plane may also be provided which has an even lower inductance than a grid network. Placing a “bypass” capacitor near the power supply terminal of the device is also used to reduce power supply droop. The by pass capacitor supplies a substantial amount of the transient load current, thereby reducing the amount of transient load current flowing through the power supply conductor. Ground bounce is reduced by using a low inductance ground conductor grid network, or a continuous ground plane having an even lower amount of inductance. Power supply and ground grids or planes are commonly placed in close proximity to one another in order to further reduce the inductances of the grids or planes.
Electromagnetic interference (EMI) is the term used to describe unwanted interference energies either conducted as currents or radiated as electromagnetic fields. High frequency components present within circuits producing digital signals having short transition times may be coupled into nearby electronic systems (e.g., radio and television circuits), disrupting proper operation of these systems. The United States Federal Communication Commission has established upper limits for the amounts of EMI products for sale in the United States may generate.
Signal circuits form current loops which radiate magnetic fields in a differential mode. Differential mode EMI is usually reduced by reducing the areas proscribed by the circuits and the magnitudes of the signal currents. Impedances of power and ground conductors create voltage drops along the conductors, causing the conductors to radiate electric fields in a common mode. Common mode EMI is typically reduced by reducing the impedances of the power and ground conductors. Reducing the impedances of the power and ground conductors thus reduces EMI as well as power supply droop and ground bounce.
Within the wide frequency range present within electronic systems with digital signals having short transition times, the electrical impedance between any two parallel conductive planes (e.g., adjacent power and ground planes) may vary widely. The parallel conductive planes may exhibit multiple electrical resonances, resulting in alternating high and low impedance values. Parallel conductive planes tend to radiate a significant amount of differential mode EMI at their boundaries (i.e., from their edges). The magnitude of differential mode EMI radiated from the edges of the parallel conductive planes varies with frequency and is directly proportional to the electrical impedance between the planes.
FIG. 1 is a perspective view of a pair of 10 in.×10 in. square conductive planes 110 and 120 separated by a fiberglass-epoxy composite dielectric layer. Each conductive plane is made of copper and is 0.0014 in. thick. The fiberglass-epoxy composite layer separating the planes has a dielectric constant of 4.0 and is 0.004 in. thick. If a 1 ampere constant current is supplied between the centers of the rectangular planes, with a varying frequency of the current, the magnitude of the steady state voltage between the centers of the rectangular planes can be determined 130.
The electrical impedance between the parallel conductive planes of FIG. 1 varies widely at frequencies above about 200 MHz. The parallel conductive planes exhibit multiple electrical resonances at frequencies between 100 MHz and 1 GHz and above, resulting in alternating high and low impedance values. The parallel conductive planes of FIG. 1 would also radiate substantial amounts of EMI at frequencies where the electrical impedance between the planes anywhere near their peripheries is high.
The above problems are currently solved in different ways at different frequency ranges. At low frequency, the power supply uses a negative feedback loop to reduce fluctuations. At higher frequencies, large value by pass (i.e. decoupling) capacitors are placed near devices. At the highest frequencies, up to about 200–300 MHz, very small by pass capacitors are placed very close to devices in an attempt to reduce their parasitic inductance, and thus high frequency impedance, to a minimum value. By Nov. 2, 1994, the practical upper limit remained around 200–300 MHz as shown by Smith [Decoupling Capacitor Calculations for CMOS Circuits; pp. 101–105 in Proceedings of 3rd Topical Meeting on Electrical Performance of Electronic Packaging of the Institute of Electrical and Electronics Engineers, Inc.].
The power distribution system was modeled as shown in FIG. 2. A switching power supply 210 supplies current and voltage to a CMOS chip load 220. In parallel with the power supply 210 and the load 220 are decoupling capacitors 215 and the PCB 225 itself, with its own capacitance. Smith [1994] teaches that decoupling capacitors are only necessary up to 200–300 MHz, as the target impedances are rarely exceeded above that frequency. This upper limit changes over time as the clock frequencies increase and the allowable voltage ripple decreases. Determining the proper values for decoupling capacitors and the optimum number of each has been a “trial and error” process, which relies on the experience of the designer. There are no known straightforward rules for choosing decoupling capacitors for all frequency ranges.
The process of choosing decoupling capacitors may be further complicated in power distribution systems that employ voltage regulators. In order for a voltage regulator to function effectively, it must be able to supply a relatively steady voltage to a load, despite any system transients that may occur. A typical voltage regulator circuit may regulate the voltage at the load by adjusting its output current. Choosing decoupling capacitors for power distribution systems including voltage regulators must include considerations of the stability and transient response of the voltage regulator circuit.